Archives

	Articles
	News
	Forums
	Polls

Write

	Article
	News

People

	Login to OC
	Lost password?
	Accounts

More

CVSget

Mirrors

Sponsors

Logos

Get account

OpenIPCore

Goals

Definition

Why

Problems

Business

Protection

Road map

Design flow

News | People | Press & Release | Introduction | Documentation | Download | Testbench | GNU Tools | Business | Mail list | Contact me

The buggy release of nnARM v1.10(zip).This version have been found to be have tons of bug,it is now correct in v1.11

The release of nnARM v1.11(zip).

The release of nnARM v1.12(zip).It contain all the source code of nnARM and the top simulation file tb_system.v in the base dictionary.

testbench release with v1.12(zip).In the asm dictionary, you can find all asembly source code that use to test my design. In the bin2asc dictionary, you can find the program that use to convert binary image file to ascii file.

The release of nnARM v1.13(zip). It can now support SWI

The release of nnARM v1.14(zip). It correct some error in ALU, mainly in BarrelShifter. At the same time, it is the first version that contain a top level synthesable module-- nnARMCore in nnARMCore.v file. many people have ask for this module several times.

testbench release with v1.14(zip)

The release of nnARM v1.15(zip). It now can support most of Thumb instruction except long branch with link.

testbench release with v1.15(zip). It contain a Thumb example program in thumbsub directory.

The new release of nnARM v1.16(zip). It now can support all Thumb instruction.

testbench release with v1.16(zip). It contain a Thumb example program in thumbsub directory that can switch into and out of Thumb state..

The new release of nnARM v1.18(zip). It now can support Normal interrupt and Fast Interrupt.

The new release of nnARM v1.19(zip). It now can support LDM/STM.

testbench release with v1.19(zip). It contain a program in block subdictionary which have many LDM/STM instructions

The new release of nnARM v1.20(zip). It now can support LDM/STM even in Thumb state.

testbench release with v1.20(zip). Because the entire testbenchs is too large, so I only upload the three new supported testbenchs: block ldm and tblock.

The new release of nnARM v1.21(zip). It now can support Wishbone bus standard.



The new release of nnARM v1.22(zip) that eleminate all tri-state signals.